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Processor Bus Cycles

Embedded software developers working in fault tolerance of the system work close to the underlying hardware. Thus a basic understanding of hardware operation is useful in developing software that interfaces directly with the hardware. In this article we will focus on some basic processor bus cycles. Understanding of bus cycle operations is useful in designing diagnostics and exception handlers.

The following processor bus cycles are described in detail:

Read Bus Cycle

1. Processor initiates a read bus cycle by floating the address of the memory location on the address lines.
2. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
3. Processor then sets the Read/Write* signal to high, i.e. read.
4. Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data.
5. The memory subsystem decodes the address and places the data on the data lines.
6. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that valid data can now be latched in.
7. Processor latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor.
8. Processor also negates the address strobe signal.
9. Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle.

Write Bus Cycle

1. Processor initiates a write bus cycle by floating the address of the memory location on the address lines.
2. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
3. Processor then sets the Read/Write* signal to low, i.e. write.
4. The processor then places the data on the data lines.
5. Now the processor asserts the data strobe signal. This signals to the memory that the processor has valid data for the memory write operation.
6. The memory subsystem decodes the address and writes the data into the addressed memory location.
7. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that data has been written to the memory.
8. Then the processor negates the data strobe, signaling that the data is no longer valid.
9. Processor also negates the address strobe signal.
10. Memory subsystem now negates the data acknowledgement signal, signaling an end to the write bus cycle.

Bus Error

Here we cover the example of a read bus cycle that fails due to the address being accessed was illegal. The processor aborts the bus cycle and initiates exception processing.

1. Processor initiates a read bus cycle by floating the address of the memory location on the address lines.
2. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
3. Processor then sets the Read/Write* signal to high, i.e. read.
4. Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data.
5. The memory subsystem decodes the address but finds that there is no memory corresponding to the address.
6. The memory subsystem, then asserts the bus error signal. This signals to the processor that an illegal address access has been attempted.
7. Processor aborts the current bus cycle and initiates bus error exception processing.
8. The current processor context is saved and the processor moves to supervisor mode.
9. The processor then fetches the bus error vector to obtain the address of the bus error handler.
10. Control is then transferred to the bus error handler.

Read-Modify-Write Bus Cycle

A read-modify-write bus cycle is nothing but a read cycle followed by a write cycle to the same address. This bus cycle is important when designing multiprocessor systems. Since the read and write operations are performed in a single bus cycle, the processor cannot loose the bus when these operations are being carried out. This type of bus cycle is used when dealing with resources managed by semaphores.

1. Processor initiates read-modify-write bus cycle by floating the address of the memory location on the address lines.
2. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
3. Processor then sets the Read/Write* signal to high, i.e. read.
4. Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data.
5. The memory subsystem decodes the address and places the data on the data lines.
6. The memory subsystem, then asserts the data acknowledge signal. This signals to the processor that valid data can now be latched in.
7. Processor latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor.
8. Memory subsystem now negates the data acknowledgement signal, signaling an end to the read part of the bus cycle.
9. Processor then sets the Read/Write* signal to low, i.e. write.
10. The processor then places the data on the data lines.
11. Now the processor asserts the data strobe signal. This signals to the memory that the processor has valid data for the memory write operation.
12. The memory subsystem decodes the address and writes the data into the addressed memory location.
13. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that data has been written into the the memory.
14. Then the processor negates the data strobe, signaling that the data is no longer valid..
15. Processor also negates the address strobe signal.
16. Memory subsystem now negates the data acknowledgement signal, signaling an end to the read-modify-write bus cycle.